View HT1380_154126.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT1380/HT1381 Serial Timekeeper Chip
Features
* * * *
Operating voltage: 2.0V~5.5V Maximum input serial clock: 500kHz at VDD=2V, 2MHz at VDD=5V Operating current: less than 400nA at 2V, less than 1.2mA at 5V TTL compatible - V : 2.0V~V IH DD+0.3V at VDD=5V - V : -0.3V~+0.8V at V IL DD=5V
* * * *
Two data transmission modes: single-byte, or burst mode Serial I/O transmission All registers store BCD format HT1380: 8-pin DIP package HT1381: 8-pin SOP package
Applications
*
Microcomputer serial clock
*
Clock and Calendar
General Description
The HT1380/HT1381 is a serial timekeeper IC which provides seconds, minutes, hours, day, date, month and year information. The number of days in each month and leap years are automatically adjusted. The HT1380/HT1381 is designed for low power consumption and can operate in two modes: one is the 12-hour mode with an AM/PM indicator, the other is the 24-hour mode. The HT1380/HT1381 has several registers to store the corresponding information with 8-bit data format. A 32768Hz crystal is required to provide the correct timing. In order to minimize the pin number, the HT1380/HT1381 use a serial I/O transmission method to interface with a microprocessor. Only three wires are required: (1) REST, (2) SCLK and (3) I/O. Data can be delivered 1 byte at a time or in a burst of up to 8 bytes.
Block Diagram
I/O SC LK D a ta S h ift R e g is te r R e a l T im e C lo c k
Pin Assignment
NC X1 X2 VSS 4 5 3 6 2 7 1 8 VDD SCLK I/O REST NC X1 X2 VSS 4 5 3 6 2 7 1 8 VDD SCLK I/O REST
REST
C om m and C o n tr o l L o g ic
O s c illa to r a n d D iv id e r C ir c u it
X1 X2
HT1380 8 D IP
HT1381 8SOP
1
October 2, 1999
HT1380/HT1381
Pad Assignment
X1 1 7 2 VDD 6
Pad Coordinates
Pad No. 1 2 3
(0 ,0 ) 5 I/O
Unit: mm X Y 775.00 494.60 -203.90 -618.30 -4.30 332.60 572.60
X2
-851.40 -851.40 -844.40 845.90 848.40 845.90 844.40
SC LK
4 5
VSS
3
6
4 REST
7
Chip size: 2010 1920 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Description
Pad No. Pad Name I/O 1 2 3 4 5 6 7 X1 X2 VSS REST I/O SCLK VDD I O I I I/O I I Internal Connection CMOS CMOS CMOS CMOS CMOS CMOS CMOS Description 32768Hz crystal input pad Oscillator output pad Ground pin Reset pin with serial transmission Data input/output pin with serial transmission Serial clock pulse pin with serial transmission Power supply pin
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V Input Voltage .................VSS-0.3V to VDD+0.3V Storage Temperature.................-50C to 125C Operating Temperature ..................0C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
2
October 2, 1999
HT1380/HT1381
D.C. Characteristics
Symbol VDD ISTB IDD IOH IOL VIH VIL fOSC fSCLK Parameter Operating Voltage Standby Current Operating Current Source Current Sink Current H Input Voltage L Input Voltage System Frequency Serial Clock Test Conditions VDD 3/4 2V 5V 2V 5V 2V 5V 2V 5V 5V 5V 5V 2V 5V Conditions 3/4 3/4 No load VOH=1.8V VOH=4.5V VOL=0.2V VOL=0.5V 3/4 3/4 32768Hz XTAL 3/4 Min. 2 3/4 3/4 3/4 3/4 -0.2 -0.5 0.7 2.0 2 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 0.7 0.7 -0.4 -1.0 1.5 4.0 3/4 3/4 32768 3/4 3/4 Max. 5.5 100 100 1.0 1.2 3/4 3/4 3/4 3/4 3/4 0.8 3/4 0.5 2 Ta=25C Unit V nA nA mA mA mA mA mA mA V V Hz MHz MHz
* ISTB is specified with SCLK, I/O, REST open. The clock halt bit must be set to logic 1 (oscillator disabled).
A.C. Characteristics
Symbol tDC tCDH tCDD tCL tCH fCLK Parameter Data to Clock Setup Clock to Data Hold Clock to Data Delay Clock Low Time Clock High Time Clock Frequency Test Conditions VDD 2V 5V 2V 5V 2V 5V 2V 5V 2V 5V 2V 5V Conditions 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
3
Ta=25C Min. 200 50 280 70 3/4 3/4 1000 250 1000 250 3/4 D.C. Max. 3/4 3/4 3/4 3/4 800 200 3/4 3/4 3/4 3/4 0.5 2.0 Unit ns ns ns ns ns MHz
October 2, 1999
HT1380/HT1381
Symbol tr tf tCC tCCH tCWH tCDZ Parameter Clock Rise and Fall Time Reset to Clock Setup Clock to Reset Hold Reset Inactive Time Reset to I/O High Impedance Test Conditions VDD 2V 5V 2V 5V 2V 5V 2V 5V 2V 5V Conditions 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Min. 3/4 3/4 4 1 240 60 4 1 3/4 3/4 Max. 2000 500 3/4 3/4 3/4 3/4 3/4 3/4 280 70 Unit ns us ns us ns
Functional Description
The HT1380/HT1381 mainly contains the following internal elements: a data shift register array to store the clock/calendar data, command control logic, oscillator circuit and read timer clock. The clock is contained in eight read/write registers as shown below. Data contained in the clock register is in binary coded decimal format. Two modes are available for transferring the data between the microprocessor and the Command byte For each data transfer, a Command Byte is initiated to specify which register is accessed. This is to determine whether a read, write, or test cycle is operated and whether a single byte or burst mode transfer is to occur. Refer to the table shown below and follow the steps to write the data to the chip. First give a Command Byte of HT1380/HT1381, and then write a data in the register. This table illustrates the correlation between Command Byte and their bits: Command Byte Function Description Select Read or Write Cycle Specify the Register to be Accessed Clock Halt Flag For IC Test Only Select Single Byte or Burst Mode Note: x stands for dont care
4 October 2, 1999
HT1380/HT1381. One is in single-byte mode ad the other is in multiple-byte mode. The HT1380/HT1381 also contains two additional bits, the clock halt bit (CH) and the write protect bit (WP). These bits control the operation of the oscillator and so data can be written to the register array. These two bits should first be specified in order to read from and write to the register array properly.
C7
C6
C5
C4
C3 A2
C2 A1 x 1
C1 A0 x 1
C0 R/W
C 1 1 0 0 0 1 1 1 x 1 1 x
HT1380/HT1381
The following table shows the register address and its data format: Register Name Seconds Minutes Hours Date Month Day Year Write Protect Range Data 00~59 00~59 01~12 00~23 01~31 01~12 01~07 00~99 00~80 WP Register Definition D7 CH 0 12\ 24 0 0 0 0 0 0 0 0 D6 D5 10 SEC 10 MIN AP 10 HR HR D4 D3 D2 D1 D0 Address A2~A0 000 001 010 011 100 101 110 111 Bit R/W W R W R W R W R W R W R W R W R Command Byte 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111
SEC MIN HOUR DATE MONTH DAY YEAR
10 DATE 0 0 10M 0
10 YEAR
ALWAYS ZERO
CH: Clock Halt bit CH=0 oscillator enabled CH=1 oscillator disabled WP: Write protect bit WP=0 register data can be written in WP=1 register data can not be written in Bit 7 of Reg2: 12/24 mode flag bit 7=1, 12-hour mode bit 7=0, 24-hour mode Bit 5 of Reg2: AM/PM mode defined AP=1 PM mode AP=0 AM mode R/W signal The LSB of the Command Byte determines whether the data in the register be read or be written to. When it is set as 0 means that a write cycle is to take place otherwise this chip will be set into the read mode.
A0~A2 A0 to A2 of the Command Byte is used to specify which registers are to be accessed. There are eight registers used to control the month data, etc., and each of these registers have to be set as a write cycle in the initial time. Burst mode When the Command Byte is 10111110 (or 10111111), the HT1380/HT1381 is configured in burst mode. In this mode the eight clock/calendar registers can be written (or read) in series, starting with bit 0 of register address 0 (see the timing on the next page). Test mode When the Command Byte is set as 1001xxx1, HT1380/HT1381 is configured in test mode. The test mode is used by Holtek only for testing purposes. If used generally, unpredictable conditions may occur.
5
October 2, 1999
HT1380/HT1381
Write protect register This register is used to prevent a write operation to any other register. Data can be written into the designated register only if the Write Protect signal (WP) is set to logic 0. The Write Protect Register should be set first before restarting the system or before writing the new data to the system, and it should set as logic 1 in the read cycle. The Write Protect bit cannot be written to in the burst mode. Clock Halt bit D7 of the Seconds Register is defined as the Clock Halt Flag (CH). When this bit is set to logic 1, the clock oscillator is stopped and the chip goes into a low-power standby mode. When this bit is written to logic 0, the clock will start. 12-hour/24-hour mode The D7 of the hour register is defined as the 12-hour or 24-hour mode select bit. When this bit is in high level, the 12-hour mode is selected otherwise its the 24-hour mode. AM-PM mode These are two functions for the D5 of the hour register determined by the value D7 of the same register. One is used in AM/PM selection on the 12-hour mode. When D5 is logic 1, it is PM, otherwise its AM. The other is used to set the second 10-hour bit (20~23 hours) on the 24-hour mode. Reset and Serial Clock control The REST pin is used to allow access data to the shift register like a toggle switch. When the REST pin is taken high, the built-in control logic is turned on and the address/command sequence can access the corresponding shift register. The REST pin is also used to terminate either single-byte or burst mode data format. The input signal of SCLK is a sequence of a falling edge followed by a rising edge and it is used to synchronize the register data whether read or write. For data input, the data must be read after the rising edge of SCLK. The data on the I/O pin becomes output mode after the falling edge of the SCLK. All data transfer terminates if the REST pin is low and the I/O pin goes to a high impedance state. The data transfer is illustrated on the next page. Data in and Data out In writing a data byte with HT1380/HT1381, the read/write should first set as R/W=0 in the Command Byte and follow with the corresponding data register on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored. Data inputs are entered starting with bit 0. In reading a data on the register of HT1380/HT1381, R/W=1 should first be entered as input. The data bit outputs on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted on the first falling edge after the last bit of the read command byte is written. Additional SCLK cycles re-transmits the data bytes as long as REST remains at high level. Data outputs are read starting with bit 0. Crystal selection A 32768Hz crystal can be directly connected to the HT1380/HT1381 via pin 2 and pin 3 (X1, X2). In order to obtain the correct frequency, two additional load capacities (C1, C2) are needed. The value of the capacity depends on how accurate the crystal is. We suggest that you can follow the table on the next page.
32768H z X1 C1 C2 X2
6
October 2, 1999
HT1380/HT1381
The following diagram shows the single and burst mode transfer:
S in g le b y te tr a n s fe r
SC LK REST 0 I/O R /W 1 A0 2 A1 3 A2 0 0 4 5 0 6 1 D A T A I/O 7 0 1 2 3 4 5 6 7
COM M AND BYTE
B u rs t m o d e tra n s fe r
SC LK REST 0 I/O R /W 1 1 2 1 3 1 1 4 1 5 0 6 1 DATA BYTE0 DATA BYTE7 7 0 7 0 7
COM M AND BYTE
The table illustrates the values suggested for capacities C1, C2 Part No. HT1380/HT1381 Crystal Error 10ppm 10~20ppm Capacity Value 5pF 8pF
Operating flowchart To initiate any transfer of data, REST is taken high and an 8-bit command byte is first loaded into the control logic to provide the register address and command information. Following the command word, the clock/calendar data is serially transferred to or from the corresponding register. The REST pin must be taken low again after the transfer operation is completed. All data enter on the rising edge of SCLK and outputs on the falling edge of SCLK. In total, 16 clock pulses are needed for a single byte mode and 72 for burst mode. Both input and output data starts with bit 0. In using the HT1380/HT1381, set first the WP and CH to 0 and wait for about 3 seconds, the oscillator will generate the clocks for internal use. Then, choose either single mode or burst mode to input the data. The read or write operating flowcharts are shown on the next page.
7
October 2, 1999
HT1380/HT1381
*
To disable the write protect (WP=0) bit and enable the oscillator (CH=0)
START
*
Single byte data transfer
*
Burst mode data transfer
START
START
S e t R E S T p in fr o m lo w to h ig h
D is a b le th e w r ite p r o te c t b it a n d e n a b le th e o s c illa to r
D is a b le th e w r ite p r o te c t b it a n d e n a b le th e o s c illa to r
In p u t th e w r ite p ro te c t c o m m a n d b y te 8 E H D is a b le th e p r o te c t b it b y s e ttin g th o f r e g is te r 7 w r ite (W P ) eMSB to z e ro *
S e t R E S T p in fr o m lo w to h ig h
S e t R E S T p in fr o m lo w to h ig h
In p u t th e c o m m a n d b y te s ta r tin g w ith b it 0
In p u t th e b u rs t m o d e c o m m a n d b y te ($ B E o r $ B F ) s ta r tin g w ith b it 0
R e s e t R E S T p in fr o m h ig h to lo w
R e a d o r w r ite th e c o r r e s p o n d in g r e g is te r d a ta b y te s ta r tin g w ith b it 0 *
Read o d a ta b y th e H T b it
r w r ite te (6 4 1381 s 0 o f re
a ll r e g is te r d a ta b its ) in ta r tin g w ith g is te r 0
S e t R E S T p in fr o m lo w to h ig h
R e s e t R E S T p in fr o m h ig h to lo w
R e s e t R E S T p in fr o m h ig h to lo w
In p u t th e w r ite c o m m a n d b y te 8 0 H
If a n o th e r r e g is te r is a c c e s s e d No END
Yes
END
E n a b le th e o s c illa to r b y s e ttin g th e M S B o f r e g is te r 0 to z e r o
R e s e t R E S T p in fr o m h ig h to lo w
END
* In reading data byte from HT1380/HT1381 register, the first data bit to be transmitted at the first falling edge after the last bit of the command byte is written.
8
October 2, 1999
HT1380/HT1381
Timing Diagrams
Read data transfer
REST tC C SC LK tD C I/O 0 COM M AND BYTE tC D H tC D D 7 0 OUTPUT DATA BYTE 7 tC D Z
Write data transfer
tC C H REST tC C SC LK tD C I/O 0 COM M AND BYTE tC D H tC L 7 0 IN P U T D A T A B Y T E 7 tC H tf tr tC W H
Application Circuits
V
DD
SC LK
X1 X2
*C 1 32768H z
mp In te rfa c e
I/O REST
*C 2 VSS
H T 1 3 8 0 /H T 1 3 8 1
*Note: The value of the capacity depends on how accurate the crystal is. Refer to the suggestion table of page 7.
9
October 2, 1999
HT1380/HT1381
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 1999 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
10
October 2, 1999

▲Up To Search▲

Price & Availability of HT1380

	To Download HT1380 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .